1. Field of the Invention
The present invention relates to semiconductor memory units, and more particularly to electronically programmable nonvolatile memory units.
2. Description of the Prior Art
Electronically erasable programmable read only memories (EEPROMS) are presently being fabricated with redundant memory locations, e.g., rows or columns, to realize an improvement in yield. Defective locations may be corrected by replacement with available redundant locations. In order that the corrections are made in a permanent manner, it is necessary that the locations of the defects or errors be stored by a nonvolatile technique, i.e., the information will be retained when power is no longer applied to the memory.
At least two existing techniques for nonvolatile storage of error locations are known. Each technique involves the separation of conductive links or fuses at appropriate locations in the memory device to permanently store the data. One technique, known as the laser link technique, involves the use of an impinging laser beam to selectively separate the fuses. A disadvantage of this technique is that it requires a substantial investment in capital equipment to implement. Another technique, known as the fusable link technique, involves burnout of a fuse by passing a relatively large current through the link. A disadvantage of this technique is that it makes inefficient usage of chip area, since substantial chip area is needed for the devices required to "blow" the fuses. Both of these techniques draw dc current unless two fuses are used per bit, making them less attractive for use with CMOS circuits.
U.S. Pat. No. 4,403,306 (Tokushige et al.) discloses a semiconductor memory operable as a static RAM or EAROM. In the EAROM operation a nonvolatile memory is provided. Nonvolatile data is stored by utilizing the hysteresis characteristics of a threshold voltage V.sub.TL of a pair of N-MNOS (N-metal nitride-oxide-silicone) transistors. One of the transistors operates as a depletion mode transistor (having a negative threshold voltage) which conducts when its gate voltage is 0 volts, while the other transistor operates as an enhancement mode transistor (having a positive threshold voltage) which is nonconductive when its gate voltage is 0 volts. The memory unit has a nominal supply voltage of +5 volts, and separate erase and write pulses of -28 volts and +28 volts, respectively, are required to erase and write nonvolatile data.
The cell count of the Tokushige et al. memory unit is relatively large, with eight transistors and two diodes comprising the cell. Since the diodes are forward biased when the unit is operating as a RAM, the diodes should be isolated separately from the other substrates. This increases the complexity of fabrication of the cell, and would at least require another mask to obtain the isolation. Since the cell voltage swing from its high to its low state is from 0 volts to (V.sub.CC minus the diode voltage drop), the noise immunity of the circuit is reduced. Dual polarity programming pulses (.+-.28 volts) are required, and the programming occurs in two steps, erase and program. The capacitor ratios would have to be carefully controlled to avoid influencing the other NMOS transistor when programming the first transistor. Thus, the Tokushige et al. memory unit appears to be of significant complexity, both in terms of construction and operation.
U.S. Pat. No. 4,132,904 (Harari) discloses a volatile/nonvolatile logic latch circuit in which a pair of circuit branches each comprise a field effect transistor and a floating gate field effect transistor connected in series. The control gates of the respective floating gate transistors are cross-coupled to the respective junctions between the series transistors in the other circuit branch. The Harari circuit not only can be programmed to assume a desired state when the circuit is turned on, but it also can be intentionally overridden so as to store complementary data.
Other nonvolatile memory devices are disclosed in U.S. Pat. Nos. 3,618,053; 4,102,348; 4,185,319; 4,207,615; 4,228,527; 4,357,685; 4,363,110; 4,387,444; and 4,408,303. However, these memory devices suffer from various disadvantages, such as requirements for sense amplifiers, complexity in fabrication, high cell count, and poor noise immunity.
It is an object of the present invention to provide a nonvolatile latch circuit which assumes the proper state when power is applied to the circuit, irrespective of the power-applying conditions, and which automatically insures against intentional or unintentional overriding.
It is a further object of the invention to provide a latch circuit which requires a minimal amount of support circuitry, such as sense amplifiers.
It is another object of the invention to provide a latch circuit which minimizes the electrical power required for circuit operation.
It is yet another object of the invention to provide a nonvolatile latch circuit having low power requirements, small cell size, high noise immunity and good data retention.